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NXP Semiconductors /MKW41Z4 /NVIC /NVIC_ISER

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Interpret as NVIC_ISER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SETENA0 0 (0)SETENA1 0 (0)SETENA2 0 (0)SETENA3 0 (0)SETENA4 0 (0)SETENA5 0 (0)SETENA6 0 (0)SETENA7 0 (0)SETENA8 0 (0)SETENA9 0 (0)SETENA10 0 (0)SETENA11 0 (0)SETENA12 0 (0)SETENA13 0 (0)SETENA14 0 (0)SETENA15 0 (0)SETENA16 0 (0)SETENA17 0 (0)SETENA18 0 (0)SETENA19 0 (0)SETENA20 0 (0)SETENA21 0 (0)SETENA22 0 (0)SETENA23 0 (0)SETENA24 0 (0)SETENA25 0 (0)SETENA26 0 (0)SETENA27 0 (0)SETENA28 0 (0)SETENA29 0 (0)SETENA30 0 (0)SETENA31

SETENA31=0, SETENA20=0, SETENA0=0, SETENA13=0, SETENA12=0, SETENA11=0, SETENA1=0, SETENA18=0, SETENA7=0, SETENA5=0, SETENA30=0, SETENA10=0, SETENA15=0, SETENA29=0, SETENA24=0, SETENA23=0, SETENA22=0, SETENA26=0, SETENA14=0, SETENA17=0, SETENA4=0, SETENA21=0, SETENA6=0, SETENA8=0, SETENA9=0, SETENA28=0, SETENA25=0, SETENA19=0, SETENA27=0, SETENA16=0, SETENA3=0, SETENA2=0

Description

Interrupt Set Enable Register

Fields

SETENA0

DMA channel 0 transfer complete/error interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 0 transfer complete/error interrupt disabled

1 (1): write: enable DMA channel 0 transfer complete/error interrupt; read: DMA channel 0 transfer complete/error interrupt enabled
SETENA1

DMA channel 1 transfer complete/error interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 1 transfer complete/error interrupt disabled

1 (1): write: enable DMA channel 1 transfer complete/error interrupt; read: DMA channel 1 transfer complete/error interrupt enabled
SETENA2

DMA channel 2 transfer complete/error interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 2 transfer complete/error interrupt disabled

1 (1): write: enable DMA channel 2 transfer complete/error interrupt; read: DMA channel 2 transfer complete/error interrupt enabled
SETENA3

DMA channel 3 transfer complete/error interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 3 transfer complete/error interrupt disabled

1 (1): write: enable DMA channel 3 transfer complete/error interrupt; read: DMA channel 3 transfer complete/error interrupt enabled
SETENA4

Reserved iv 20 interrupt set-enable bit

0 (0): write: no effect; read: Reserved iv 20 interrupt disabled

1 (1): write: enable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
SETENA5

Flash command complete and read collision interrupt set-enable bit

0 (0): write: no effect; read: Flash command complete and read collision interrupt disabled

1 (1): write: enable Flash command complete and read collision interrupt; read: Flash command complete and read collision interrupt enabled
SETENA6

Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt set-enable bit

0 (0): write: no effect; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt disabled

1 (1): write: enable Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt enabled
SETENA7

Low Leakage Wakeup interrupt set-enable bit

0 (0): write: no effect; read: Low Leakage Wakeup interrupt disabled

1 (1): write: enable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
SETENA8

Inter-Integrated Circuit 0 interrupt set-enable bit

0 (0): write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

1 (1): write: enable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
SETENA9

Inter-Integrated Circuit 1 interrupt set-enable bit

0 (0): write: no effect; read: Inter-Integrated Circuit 1 interrupt disabled

1 (1): write: enable Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt enabled
SETENA10

Serial Peripheral Interface 0 interrupt set-enable bit

0 (0): write: no effect; read: Serial Peripheral Interface 0 interrupt disabled

1 (1): write: enable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
SETENA11

Touch Sensing Input interrupt set-enable bit

0 (0): write: no effect; read: Touch Sensing Input interrupt disabled

1 (1): write: enable Touch Sensing Input interrupt; read: Touch Sensing Input interrupt enabled
SETENA12

LPUART0 status and error interrupt set-enable bit

0 (0): write: no effect; read: LPUART0 status and error interrupt disabled

1 (1): write: enable LPUART0 status and error interrupt; read: LPUART0 status and error interrupt enabled
SETENA13

True Random Number Generator interrupt set-enable bit

0 (0): write: no effect; read: True Random Number Generator interrupt disabled

1 (1): write: enable True Random Number Generator interrupt; read: True Random Number Generator interrupt enabled
SETENA14

Carrier modulator transmitter interrupt set-enable bit

0 (0): write: no effect; read: Carrier modulator transmitter interrupt disabled

1 (1): write: enable Carrier modulator transmitter interrupt; read: Carrier modulator transmitter interrupt enabled
SETENA15

Analog-to-Digital Converter 0 interrupt set-enable bit

0 (0): write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled

1 (1): write: enable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
SETENA16

DMA channel 0 - 31 error interrupt set-enable bit

0 (0): write: no effect; read: DMA channel 0 - 31 error interrupt disabled

1 (1): write: enable DMA channel 0 - 31 error interrupt; read: DMA channel 0 - 31 error interrupt enabled
SETENA17

Timer/PWM module 0 interrupt set-enable bit

0 (0): write: no effect; read: Timer/PWM module 0 interrupt disabled

1 (1): write: enable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
SETENA18

Timer/PWM module 1 interrupt set-enable bit

0 (0): write: no effect; read: Timer/PWM module 1 interrupt disabled

1 (1): write: enable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
SETENA19

Timer/PWM module 2 interrupt set-enable bit

0 (0): write: no effect; read: Timer/PWM module 2 interrupt disabled

1 (1): write: enable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled
SETENA20

Real-time counter interrupt set-enable bit

0 (0): write: no effect; read: Real-time counter interrupt disabled

1 (1): write: enable Real-time counter interrupt; read: Real-time counter interrupt enabled
SETENA21

RTC seconds interrupt set-enable bit

0 (0): write: no effect; read: RTC seconds interrupt disabled

1 (1): write: enable RTC seconds interrupt; read: RTC seconds interrupt enabled
SETENA22

Periodic Interrupt Timer interrupt set-enable bit

0 (0): write: no effect; read: Periodic Interrupt Timer interrupt disabled

1 (1): write: enable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled
SETENA23

LTC0 interrupt set-enable bit

0 (0): write: no effect; read: LTC0 interrupt disabled

1 (1): write: enable LTC0 interrupt; read: LTC0 interrupt enabled
SETENA24

Radio 0 interrupt set-enable bit

0 (0): write: no effect; read: Radio 0 interrupt disabled

1 (1): write: enable Radio 0 interrupt; read: Radio 0 interrupt enabled
SETENA25

Digital to Analog Converter interrupt set-enable bit

0 (0): write: no effect; read: Digital to Analog Converter interrupt disabled

1 (1): write: enable Digital to Analog Converter interrupt; read: Digital to Analog Converter interrupt enabled
SETENA26

Radio 1 interrupt set-enable bit

0 (0): write: no effect; read: Radio 1 interrupt disabled

1 (1): write: enable Radio 1 interrupt; read: Radio 1 interrupt enabled
SETENA27

Multipurpose Clock Generator interrupt set-enable bit

0 (0): write: no effect; read: Multipurpose Clock Generator interrupt disabled

1 (1): write: enable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled
SETENA28

Low-Power Timer 0 interrupt set-enable bit

0 (0): write: no effect; read: Low-Power Timer 0 interrupt disabled

1 (1): write: enable Low-Power Timer 0 interrupt; read: Low-Power Timer 0 interrupt enabled
SETENA29

Serial Peripheral Interface 1 interrupt set-enable bit

0 (0): write: no effect; read: Serial Peripheral Interface 1 interrupt disabled

1 (1): write: enable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled
SETENA30

Pin detect Port A interrupt set-enable bit

0 (0): write: no effect; read: Pin detect Port A interrupt disabled

1 (1): write: enable Pin detect Port A interrupt; read: Pin detect Port A interrupt enabled
SETENA31

Pin detect Port B and C interrupt set-enable bit

0 (0): write: no effect; read: Pin detect Port B and C interrupt disabled

1 (1): write: enable Pin detect Port B and C interrupt; read: Pin detect Port B and C interrupt enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of the copyright holder nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data